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authorAnkit Nautiyal <ankit.k.nautiyal@intel.com>2025-03-24 16:32:43 +0300
committerAnkit Nautiyal <ankit.k.nautiyal@intel.com>2025-03-25 18:47:25 +0300
commit423f9d7c52235a7b63f5b03655a722ee3c1cdb24 (patch)
tree8ebb42f386e357fa8ed7bf5392028bb6292a4e1b /tools/perf/scripts/python/export-to-postgresql.py
parent704bd24d010e1491bc63b738145be4827e235e22 (diff)
downloadlinux-423f9d7c52235a7b63f5b03655a722ee3c1cdb24.tar.xz
drm/i915/display: Move vrr.guardband/pipeline_full out of !fastset block
Since the vrr.guardband can now change for platforms that always use the VRR Timing Generator, and it is unsafe to reprogram the guardband on the fly, move the guardband and pipeline_full checks from the pure !fastboot path and add a check for intel_vrr_always_use_vrr_tg(). For older platforms the vrr.guardband change happens when VRR Timing generator is off. For the platforms that always use the VRR Timing Generator, this will prevent reprogramming the vrr.guardband without a full modeset. However, this will disrupt LRR functionality for these platforms. v2: Modify the check to avoid breaking the LRR on older platform. (Ville) v3: Correct the oversight of not removing the lines from the original location. (Ville) Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://lore.kernel.org/r/20250324133248.4071909-12-ankit.k.nautiyal@intel.com
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