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authorGeert Uytterhoeven <geert+renesas@glider.be>2024-06-20 16:57:34 +0300
committerGeert Uytterhoeven <geert+renesas@glider.be>2024-07-01 12:35:07 +0300
commit4036bae6dfd782d414040e7d714abc525b2e8792 (patch)
tree6f4aedb94d2428d4ab15912af72f56582da9aada /tools/perf/scripts/python/export-to-postgresql.py
parent6775165fc95052a03acc91e25bc20fcf286910a7 (diff)
downloadlinux-4036bae6dfd782d414040e7d714abc525b2e8792.tar.xz
arm64: dts: renesas: r9a07g043u: Add missing hypervisor virtual timer IRQ
Add the missing fifth interrupt to the device node that represents the ARM architected timer. While at it, add an interrupt-names property for clarity, Fixes: cf40c9689e5109bf ("arm64: dts: renesas: Add initial DTSI for RZ/G2UL SoC") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/15cc7a7522b1658327a2bd0c4990d0131bbcb4d7.1718890849.git.geert+renesas@glider.be
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