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authorWenjing Liu <Wenjing.Liu@amd.com>2017-08-24 00:02:34 +0300
committerAlex Deucher <alexander.deucher@amd.com>2017-09-27 01:17:08 +0300
commit1cf49dea28dfc76f0816a4bc73c2ab975c72f55d (patch)
treeb10986b0a1c45c80194fdf703eb2a07cd058176d /tools/perf/scripts/python/export-to-postgresql.py
parent156590454259a19d1709fab2ff7d59870574e822 (diff)
downloadlinux-1cf49dea28dfc76f0816a4bc73c2ab975c72f55d.tar.xz
drm/amd/display: do not reset lane count in EQ fallback
[Description] According to DP1.4 specs we should not reset lane count back when falling back in failing EQ training. This causes PHY test pattern compliance to fail as infinite LT when LT fails EQ to 4 RBR and fails CR in a loop. Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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