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authorJani Nikula <jani.nikula@intel.com>2019-03-05 16:52:14 +0300
committerJani Nikula <jani.nikula@intel.com>2019-03-08 14:25:31 +0300
commit1b61c4a3eea2bead6725b6907616684497ff8765 (patch)
tree6ac0727027ded0118d3f9d6a43cca36ebd588476 /tools/perf/scripts/python/export-to-postgresql.py
parent7d6ce55887a44c15c6df29e883d0ea567c8ac55c (diff)
downloadlinux-1b61c4a3eea2bead6725b6907616684497ff8765.tar.xz
drm/i915/dp: deconflate PPS unlock from divisor register
PPS locking is a thing on pre-DDI, up to and including CPT and PPT. The PPS divisor register exists up to gen 9 BC, replaced by a field in the control register starting from gen 9 LP, i.e. BXT, GLK, and CNP on. Commit b0a08bec9631 ("drm/i915/bxt: eDP Panel Power sequencing") stopped using the divisor register, but inadvertently conflated the PPS unlock in the change. No longer doing the unlocking was the right thing to do, however we should've stopped already at LPT (or DDI platforms). Deconflate the two. Arguably this could be moved away from here altogether, but this is the minimally intrusive change for now. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190305135215.29862-1-jani.nikula@intel.com
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