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| author | Arun R Murthy <arun.r.murthy@intel.com> | 2023-03-02 11:15:32 +0300 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2023-03-21 17:17:20 +0300 |
| commit | 1a324a40b452ae0a57676369c0a0150674728853 (patch) | |
| tree | b8120a8c3e4d55b25dc2334fbe124bbaa48f9aa1 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 562334d22a05a4793a620a9ef02516f3b8da9ec5 (diff) | |
| download | linux-1a324a40b452ae0a57676369c0a0150674728853.tar.xz | |
i915/display/dp: SDP CRC16 for 128b132b link layer
Enable SDP error detection configuration, this will set CRC16 in
128b/132b link layer.
For Display version 13 a hardware bit31 in register VIDEO_DIP_CTL is
added to enable/disable SDP CRC applicable for DP2.0 only, but the
default value of this bit will enable CRC16 in 128b/132b hence
skipping this write.
Corrective actions on SDP corruption is yet to be defined.
v2: Moved the CRC enable to link training init(Jani N)
v3: Moved crc enable to ddi pre enable <Jani N>
v4: Separate function for SDP CRC16 (Jani N)
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230302081532.765821-3-arun.r.murthy@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions