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authorVinod Govindapillai <vinod.govindapillai@intel.com>2025-03-30 20:26:16 +0300
committerVinod Govindapillai <vinod.govindapillai@intel.com>2025-03-31 14:36:50 +0300
commit010363c4618920838ca8777fdabd46871d289bf9 (patch)
tree2728118a3c6ac777e160f01e939abc2e0068ea7b /tools/perf/scripts/python/export-to-postgresql.py
parent9900e35a3ab14e1dcd5987b7ea13150e9ba2dc02 (diff)
downloadlinux-010363c4618920838ca8777fdabd46871d289bf9.tar.xz
drm/i915/display: implement wa_18038517565
Disable FBC compressor clock gating before enabling FBC and clear it after disabling FBC. v2: update the DG2 registers for this wa v3: use local variable and single line reg definition (Jani) Bspec: 74212, 72197, 69741, 65555 Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Link: https://lore.kernel.org/r/20250330172616.718188-1-vinod.govindapillai@intel.com
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