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| author | Jesse Barnes <jbarnes@virtuousgeek.org> | 2012-10-26 20:42:42 +0400 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-11-12 02:51:36 +0400 |
| commit | 9a28977181724ebbd9bdc45291cf29da55a729ee (patch) | |
| tree | d83f779436fcaab0b445c64ee50252269ba6b211 /tools/perf/scripts/python/event_analyzing_sample.py | |
| parent | 12f3382bc0262e981a2e58aca900cbbdbbe66825 (diff) | |
| download | linux-9a28977181724ebbd9bdc45291cf29da55a729ee.tar.xz | |
drm/i915: TLB invalidation with MI_FLUSH_DW requires a post-sync op v3
So store into the scratch space of the HWS to make sure the invalidate
occurs.
v2: use GTT address space for store, clean up #defines (Chris)
v3: use correct #define in blt ring flush (Chris)
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Antti Koskipää <antti.koskipaa@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
References: https://bugs.launchpad.net/ubuntu/+source/xserver-xorg-video-intel/+bug/1063252
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tools/perf/scripts/python/event_analyzing_sample.py')
0 files changed, 0 insertions, 0 deletions