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| author | Conor Dooley <conor.dooley@microchip.com> | 2022-04-13 10:58:31 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2022-04-23 04:40:11 +0300 |
| commit | 3ebb9fdf466a246bb17164b70039dce584a0b959 (patch) | |
| tree | ae147fc6ca7cfa2c222db4bc44d9a62ad6be805b /tools/perf/scripts/python/event_analyzing_sample.py | |
| parent | 2b6190c804238cbdca4e4fbe20304151203a3837 (diff) | |
| download | linux-3ebb9fdf466a246bb17164b70039dce584a0b959.tar.xz | |
dt-bindings: clk: mpfs document msspll dri registers
As there are two sections of registers that are responsible for clock
configuration on the PolarFire SoC: add the dynamic reconfiguration
interface section to the binding & describe what each of the sections
are used for.
Fixes: 2145bb687e3f ("dt-bindings: clk: microchip: Add Microchip PolarFire host binding")
Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20220413075835.3354193-5-conor.dooley@microchip.com
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/event_analyzing_sample.py')
0 files changed, 0 insertions, 0 deletions