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authorBiju Das <biju.das.jz@bp.renesas.com>2022-03-15 17:26:38 +0300
committerGeert Uytterhoeven <geert+renesas@glider.be>2022-04-04 12:00:51 +0300
commit3f285c301cd788164fa776e1f95458c56e68a6ee (patch)
treed5a75aa91b7f32cb2522d939b03843b0c07194df /tools/perf/scripts/python/check-perf-trace.py
parent3123109284176b1532874591f7c81f3837bbdc17 (diff)
downloadlinux-3f285c301cd788164fa776e1f95458c56e68a6ee.tar.xz
dt-bindings: power: renesas,rzg2l-sysc: Document RZ/G2UL SoC
Add DT binding documentation for SYSC controller found on RZ/G2UL SoC's. SYSC controller found on the RZ/G2UL SoC is almost identical to one found on the RZ/G2L SoC's only difference being that the RZ/G2UL has only CA55 core0 reset vector address configuration register. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220315142644.17660-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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