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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2014-03-05 15:05:47 +0400 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-03-06 00:30:44 +0400 |
| commit | 8f670bb15a69e1186098454beb1b43dc1d923a24 (patch) | |
| tree | 175f076b4559206efa56e321ca74c165950f0ab7 /tools/perf/scripts/python/bin | |
| parent | 2adb6db8d9fb0f94173a4cba6e1dcb8585f1a928 (diff) | |
| download | linux-8f670bb15a69e1186098454beb1b43dc1d923a24.tar.xz | |
drm/i915: Unify CHICKEN_PIPESL_1 register definitions
We have two names for the same register CHICKEN_PIPESL_1 and
HSW_PIPE_SLICE_CHICKEN_1. Unify it to just one.
Also rename the FBCQ disable bit to resemble the name we've
given to a similar bit on earlier platforms.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions