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| author | Isabel Zhang <isabel.zhang@amd.com> | 2020-10-16 17:55:54 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-11-02 23:29:59 +0300 |
| commit | 685b4d8142dcbf11b817f74c2bc5b94eca7ee7f2 (patch) | |
| tree | c935b66c392d02b88a382e95d208f5b4b5784cc4 /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | 850d2fcf3e346a35e4e59e310b867e90e3ef8e5a (diff) | |
| download | linux-685b4d8142dcbf11b817f74c2bc5b94eca7ee7f2.tar.xz | |
drm/amd/display: Force prefetch mode to 0
[Why]
On APU should be always using prefetch mode 0.
Currently, sometimes prefetch mode 1 is being
used causing system to hard hang due to
minTTUVBlank being too low.
[How]
Any ASIC running DCN21 will by default allow
self refresh and mclk switch. This sets both
min and max prefetch mode to 0 by default.
Signed-off-by: Isabel Zhang <isabel.zhang@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions