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| author | Daniel Scally <dan.scally@ideasonboard.com> | 2025-10-10 12:43:10 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-10-14 11:50:30 +0300 |
| commit | 0f537c41831aea18e54d889350e706e221beda63 (patch) | |
| tree | 63d0baad431fc508a51891ee1d2f2944a01bb627 /tools/perf/scripts/python/arm-cs-trace-disasm.py | |
| parent | e43b186df5c4635059f6213d100c9314c1570d02 (diff) | |
| download | linux-0f537c41831aea18e54d889350e706e221beda63.tar.xz | |
clk: renesas: r9a09g057: Add clock and reset entries for ISP
Add entries detailing the clocks and resets for the ISP in the
RZ/V2H(P) SoC.
Signed-off-by: Daniel Scally <dan.scally@ideasonboard.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251010-rzv2h_isp_clk-v2-1-2c8853a9af7c@ideasonboard.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/arm-cs-trace-disasm.py')
0 files changed, 0 insertions, 0 deletions