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| author | Charlie Jenkins <charlie@rivosinc.com> | 2024-11-09 02:47:36 +0300 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2024-11-13 01:45:26 +0300 |
| commit | 0eb512779d642b21ced83778287a0f7a3ca8f2a1 (patch) | |
| tree | 7f15cdf45952c986d13287acb6c34dcf6d38a309 /tools/perf/scripts/python/arm-cs-trace-disasm.py | |
| parent | 64f7b77f0bd9271861ed9e410e9856b6b0b21c48 (diff) | |
| download | linux-0eb512779d642b21ced83778287a0f7a3ca8f2a1.tar.xz | |
riscv: Fix default misaligned access trap
Commit d1703dc7bc8e ("RISC-V: Detect unaligned vector accesses
supported") removed the default handlers for handle_misaligned_load()
and handle_misaligned_store(). When the kernel is compiled without
RISCV_SCALAR_MISALIGNED, these handlers are never defined, causing
compilation errors.
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
Fixes: d1703dc7bc8e ("RISC-V: Detect unaligned vector accesses supported")
Reviewed-by: Jesse Taube <mr.bossman075@gmail.com>
Link: https://lore.kernel.org/r/20241108-fix_handle_misaligned_load-v2-1-91d547ce64db@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'tools/perf/scripts/python/arm-cs-trace-disasm.py')
0 files changed, 0 insertions, 0 deletions