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authorGrzegorz Nitka <grzegorz.nitka@intel.com>2026-06-07 21:30:45 +0300
committerJakub Kicinski <kuba@kernel.org>2026-06-13 23:24:36 +0300
commite075d7768386235f4a08d7e04d02c90ce51fd64e (patch)
tree36eec0df6e54e6aef59f9304a65674221f2cffb0 /tools/lib/python
parent4128bda8fc1d6c845a5259328193aaec4529b345 (diff)
downloadlinux-e075d7768386235f4a08d7e04d02c90ce51fd64e.tar.xz
ice: implement E825 TX ref clock control and TXC hardware sync status
Build on the previously introduced TXC DPLL framework and implement full TX reference clock control and hardware-backed synchronization status reporting for E825 devices. E825 firmware may accept or override TX reference clock requests based on device-wide routing constraints and link conditions. Because the final selection becomes visible only after a link-up event, the driver splits the observation into two complementary signals: - TXCLK pin state reflects the requested TX reference clock (pf->ptp.port.tx_clk_req). After a link-up, the value is reconciled against the SERDES reference selector by ice_txclk_update_and_notify(); if firmware or auto-negotiation selected a different clock, tx_clk_req is overwritten so that pin state converges to the actual hardware selection. - TXC DPLL lock status reflects hardware synchronization: * LOCKED when an external TX reference is in use * UNLOCKED when falling back to ENET/TXCO, or when a requested external reference has not (yet) been accepted by hardware. Userspace observing only pin state therefore sees user intent, while lock status is the authoritative indicator of whether the requested clock is actually selected and synchronizing. This matches the DPLL subsystem model where pin state describes topology and device lock status describes signal quality. TX reference selection topology: - External references (SYNCE, EREF0) are represented as TXCLK pins - The internal ENET/TXCO clock has no pin representation; when selected, all TXCLK pins are reported DISCONNECTED With this change, TX reference clocks on E825 devices can be reliably selected, observed via standard DPLL interfaces, and monitored for effective synchronization through TXC DPLL lock status. Reviewed-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com> Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com> Link: https://patch.msgid.link/20260607183045.1213735-14-grzegorz.nitka@intel.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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