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authorInbaraj E <inbaraj.e@samsung.com>2025-08-14 17:09:33 +0300
committerKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>2025-08-18 11:46:36 +0300
commit1a713bd3b0c60d826bdde633919bedc1fd38df4d (patch)
treed28082bd04c5007536dc6ab76d1f51504c6ab5e5 /tools/lib/python
parent5576d8098052952a6c95af86ad3dcb341554ac75 (diff)
downloadlinux-1a713bd3b0c60d826bdde633919bedc1fd38df4d.tar.xz
clk: samsung: fsd: Add clk id for PCLK and PLL in CAM_CSI block
Add clock id for PCLK and PLL. These clock id will be used for operation of CSI driver. PCLK is AXI2APB clock used for register access. PLL clock is main clock source for CAM_CSI block. Signed-off-by: Inbaraj E <inbaraj.e@samsung.com> Link: https://lore.kernel.org/r/20250814140943.22531-3-inbaraj.e@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Diffstat (limited to 'tools/lib/python')
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