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| author | Shiji Yang <yangshiji66@outlook.com> | 2026-02-24 11:51:02 +0300 |
|---|---|---|
| committer | Uwe Kleine-König <ukleinek@kernel.org> | 2026-05-23 19:24:28 +0300 |
| commit | c84291ce0e09db9377d7177e4c82424e42d26c8f (patch) | |
| tree | bad2fb9973d768452e8a3935d518eab67c8f3fd6 /tools/lib/python/kdoc/python_version.py | |
| parent | 88c6c956fa310117638e41d4831b20074dfff2ba (diff) | |
| download | linux-c84291ce0e09db9377d7177e4c82424e42d26c8f.tar.xz | |
pwm: mediatek: correct mt7628 clock source setting
PWMCON register Bit(3) is used to configure whether to pre divide
the clock source. Most revisions clear this bit to disable frequency
division. However, mt7628 needs to set this bit. Hence, we introduce
a new clksel_fixup flag to correctly configure the clock source for
mt7628.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://patch.msgid.link/OS7PR01MB136020DA816E8D601D5BA8BF4BC74A@OS7PR01MB13602.jpnprd01.prod.outlook.com
Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>
Diffstat (limited to 'tools/lib/python/kdoc/python_version.py')
0 files changed, 0 insertions, 0 deletions