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| author | Wei-Lin Chang <weilin.chang@arm.com> | 2026-05-05 17:47:35 +0300 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2026-05-06 19:08:39 +0300 |
| commit | 8d9b9d985ad3a81c751a6b97edaf1d3c0780af7c (patch) | |
| tree | 98d471fec989179e40f80d8ceab58b336f88d656 /tools/lib/python/feat/parse_features.py | |
| parent | 1f7305d87aa23db2579df222eba504a333c2c978 (diff) | |
| download | linux-8d9b9d985ad3a81c751a6b97edaf1d3c0780af7c.tar.xz | |
KVM: arm64: nv: Consider the DS bit when translating TCR_EL2
When running an nVHE L1, TCR_EL2 is mapped to TCR_EL1. Writes to the
register are trapped and written to TCR_EL1 after a translation.
Booting an nVHE L1 with 52-bit VA isn't working because the translation
was ignoring the DS bit set by the guest, hence causing repeating level
0 faults. Add it in the translation function.
Signed-off-by: Wei-Lin Chang <weilin.chang@arm.com>
Link: https://patch.msgid.link/20260505144735.1496530-1-weilin.chang@arm.com
Signed-off-by: Marc Zyngier <maz@kernel.org>
Diffstat (limited to 'tools/lib/python/feat/parse_features.py')
0 files changed, 0 insertions, 0 deletions