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authorMiquel Raynal <miquel.raynal@bootlin.com>2023-04-19 21:38:10 +0300
committerMiquel Raynal <miquel.raynal@bootlin.com>2023-04-19 21:38:20 +0300
commit38f1aa5566730cdc5e09ec982c80489d87f0f0a7 (patch)
tree853cc489bbb113b86c0cf22dd4277d0b7fd9e59a /tools/include/linux/bits.h
parente6026eb080fa1c1ef6eec24567b733809a5e3018 (diff)
parentdf6def86b9dcbc3e8ed4964c7b79b70c9b0c3040 (diff)
downloadlinux-38f1aa5566730cdc5e09ec982c80489d87f0f0a7.tar.xz
Merge tag 'spi-nor/for-6.4' into mtd/next
SPI NOR core changes: * introduce Read While Write support for flashes featuring several banks * set the 4-Byte Address Mode method based on SFDP data * allow post_sfdp hook to return errors * parse SCCR MC table and introduce support for multi-chip devices SPI NOR manufacturer drivers changes: * macronix: add support for mx25uw51245g with RWW * spansion: - determine current address mode at runtime as it can be changed in a non-volatile way and differ from factory defaults or from what SFDP advertises. - enable JFFS2 write buffer mode for few ECC'd NOR flashes: S25FS256T, s25hx and s28hx - add support for s25hl02gt and s25hs02gt Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Diffstat (limited to 'tools/include/linux/bits.h')
-rw-r--r--tools/include/linux/bits.h1
1 files changed, 0 insertions, 1 deletions
diff --git a/tools/include/linux/bits.h b/tools/include/linux/bits.h
index 87d112650dfb..7c0cf5031abe 100644
--- a/tools/include/linux/bits.h
+++ b/tools/include/linux/bits.h
@@ -6,7 +6,6 @@
#include <vdso/bits.h>
#include <asm/bitsperlong.h>
-#define BIT_ULL(nr) (ULL(1) << (nr))
#define BIT_MASK(nr) (UL(1) << ((nr) % BITS_PER_LONG))
#define BIT_WORD(nr) ((nr) / BITS_PER_LONG)
#define BIT_ULL_MASK(nr) (ULL(1) << ((nr) % BITS_PER_LONG_LONG))