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| author | Bjorn Andersson <bjorn.andersson@oss.qualcomm.com> | 2025-08-12 06:11:34 +0300 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2025-08-12 17:59:53 +0300 |
| commit | 5a5f478ed7c7394dadb65a96f409e0749caefed5 (patch) | |
| tree | c00614f45f66c60c372cd68beac2a53596961c1c /tools/docs/parse-headers.py | |
| parent | ccdba33f5c32bca06f5186eedeb15944f84db996 (diff) | |
| download | linux-5a5f478ed7c7394dadb65a96f409e0749caefed5.tar.xz | |
clk: qcom: dispcc-sc7280: Add dispcc resets
Like many other platforms the sc7280 display clock controller provides
a couple of resets for the display subsystem. In particular the
MDSS_CORE_BCR is useful to reset the display subsystem to a known state
during boot, so add these.
Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250811-sc7280-mdss-reset-v1-2-83ceff1d48de@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'tools/docs/parse-headers.py')
0 files changed, 0 insertions, 0 deletions