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| author | Xin Li <xin@zytor.com> | 2025-08-05 23:22:19 +0300 |
|---|---|---|
| committer | Sean Christopherson <seanjc@google.com> | 2025-08-19 21:59:44 +0300 |
| commit | 3c7cb84145336721eddc86982532df84bbc80853 (patch) | |
| tree | 5d480c891ee15c15e5614414a6a0f9517eb36fdf /tools/docs/parse-headers.py | |
| parent | 6c3d4b917995a17f515943ccd39ba11b81753b0d (diff) | |
| download | linux-3c7cb84145336721eddc86982532df84bbc80853.tar.xz | |
x86/cpufeatures: Add a CPU feature bit for MSR immediate form instructions
The immediate form of MSR access instructions are primarily motivated
by performance, not code size: by having the MSR number in an immediate,
it is available *much* earlier in the pipeline, which allows the
hardware much more leeway about how a particular MSR is handled.
Use a scattered CPU feature bit for MSR immediate form instructions.
Suggested-by: Borislav Petkov (AMD) <bp@alien8.de>
Signed-off-by: Xin Li (Intel) <xin@zytor.com>
Link: https://lore.kernel.org/r/20250805202224.1475590-2-seanjc@google.com
Signed-off-by: Sean Christopherson <seanjc@google.com>
Diffstat (limited to 'tools/docs/parse-headers.py')
0 files changed, 0 insertions, 0 deletions