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| author | Akhil P Oommen <akhilpo@oss.qualcomm.com> | 2026-03-05 21:21:16 +0300 |
|---|---|---|
| committer | Rob Clark <robin.clark@oss.qualcomm.com> | 2026-03-06 00:49:50 +0300 |
| commit | 7e459c41264fdd87b096ede8da796a302d569722 (patch) | |
| tree | 3c21d6a41f2743abf94b8a28fe5b028d1caba18f /scripts | |
| parent | e4eb6e4dd6348dd00e19c2275e3fbaed304ca3bd (diff) | |
| download | linux-7e459c41264fdd87b096ede8da796a302d569722.tar.xz | |
drm/msm/a8xx: Fix ubwc config related to swizzling
To disable l2/l3 swizzling in A8x, set the respective bits in both
GRAS_NC_MODE_CNTL and RB_CCU_NC_MODE_CNTL registers. This is required
for Glymur where it is recommended to keep l2/l3 swizzling disabled.
Fixes: 288a93200892 ("drm/msm/adreno: Introduce A8x GPU Support")
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Message-ID: <20260305-a8xx-ubwc-fix-v1-1-d99b6da4c5a9@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Diffstat (limited to 'scripts')
0 files changed, 0 insertions, 0 deletions