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| author | Pandiyan, Dhinakaran <dhinakaran.pandiyan@intel.com> | 2017-03-15 01:45:56 +0300 |
|---|---|---|
| committer | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2017-03-22 22:05:11 +0300 |
| commit | 8cbeb06dc6b584009d7492c667a3c9a4b96cdefa (patch) | |
| tree | 3d49810e2a09f98375ca222ca4e3bfc204b664b1 /scripts/stackusage | |
| parent | 78cfa580f81e69857815c59c8908aee454726da1 (diff) | |
| download | linux-8cbeb06dc6b584009d7492c667a3c9a4b96cdefa.tar.xz | |
drm/i915: Implement cdclk restrictions based on Azalia BCLK
According to BSpec, "The CD clock frequency must be at least twice the
frequency of the Azalia BCLK." and BCLK is configured to 96 MHz by
default. This check is needed because BXT and GLK support cdclk
frequencies less than 192 MHz.
v2: Include other Gen9 platforms too for completeness.(Paulo)
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1489531556-2926-1-git-send-email-dhinakaran.pandiyan@intel.com
Diffstat (limited to 'scripts/stackusage')
0 files changed, 0 insertions, 0 deletions