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| author | Krishna chaitanya chundru <quic_krichai@quicinc.com> | 2024-10-24 16:28:49 +0300 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2024-10-24 18:40:06 +0300 |
| commit | 267643b3e3a4e6cb7996da77f6d7f89ed8f5d554 (patch) | |
| tree | 411285779c929e5084143d701e834fcae856f785 /scripts/lib/kdoc/kdoc_files.py | |
| parent | 06d6fe987bda731b7c6619495aebedf638d37f2d (diff) | |
| download | linux-267643b3e3a4e6cb7996da77f6d7f89ed8f5d554.tar.xz | |
arm64: dts: qcom: qcs6490-rb3gen2: Add PCIe nodes
Enable PCIe1 controller and its corresponding PHY nodes on
qcs6490-rb3g2 platform.
SMMU v2 has limited SID's to assign dynamic SID's with the existing
logic. For now, use static iommu-map table assigning unique SID's for
each port as dynamic approach needs boarder community discussions.
PCIe switch connected to this board has 3 downstream ports and
to the one of the downstream an embedded ethernet is connected.
Assign unique SID for each downstream port and to embedded ethernet,
and also reserve a SID for the endpoints which are going to be
connected to the other two downstream ports.
As this PCIe switch is present in this platform only update iommu-map
in this platform only as other board variants might have different
PCIe topology and might need different mapping.
Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
Link: https://lore.kernel.org/r/20241024-enable_pcie-v2-1-e5a6f5da74e4@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'scripts/lib/kdoc/kdoc_files.py')
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