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| author | Li Ming <ming.li@zohomail.com> | 2025-03-17 10:01:24 +0300 |
|---|---|---|
| committer | Dave Jiang <dave.jiang@intel.com> | 2025-03-20 21:28:45 +0300 |
| commit | aae0594a7053c60b82621136257c8b648c67b512 (patch) | |
| tree | 38e5084de7acb73883ce94893c4b4e0de8f9973d /scripts/lib/abi/helpers.py | |
| parent | 3b5d43245f0a56390baaa670e1b6d898772266b3 (diff) | |
| download | linux-aae0594a7053c60b82621136257c8b648c67b512.tar.xz | |
cxl/region: Fix the first aliased address miscalculation
In extended linear cache(ELC) case, cxl_port_get_spa_cache_alias() helps
to get the aliased address of a SPA, it considers the first address in
CXL memory range is "region start + region cache size + 1", but it
should be "region start + region cache size".
So if a SPA is equal to "region start + region cache size", its aliased
address should be "SPA - region cache size".
Signed-off-by: Li Ming <ming.li@zohomail.com>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Link: https://patch.msgid.link/20250317070124.815028-1-ming.li@zohomail.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Diffstat (limited to 'scripts/lib/abi/helpers.py')
0 files changed, 0 insertions, 0 deletions