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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2026-04-30 12:34:06 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2026-05-11 12:03:50 +0300 |
| commit | 43d2cd6f61ffc04be19f4c7542554e4d28786a17 (patch) | |
| tree | 9bb1bcd3c280c3e93fb79b65f1f73d4b4020b1f3 /scripts/include | |
| parent | 9c45ef9a84bd18cbd2052d5e64b2144018f5bb32 (diff) | |
| download | linux-43d2cd6f61ffc04be19f4c7542554e4d28786a17.tar.xz | |
dt-bindings: pinctrl: renesas: Document RZ/G3L SoC
Add documentation for the pin controller found on the Renesas RZ/G3L
(R9A08G046) SoC. The RZ/G3L PFC is similar to the RZ/G3S SoC but has
more pins.
Also add header file similar to RZ/G3E and RZ/V2H as it has alpha
numeric ports.
Document renesas,clonech property for controlling clone channel
control register located on SYSC IP block on RZ/G3L SoC.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260430093422.74812-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'scripts/include')
0 files changed, 0 insertions, 0 deletions
