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| author | Niravkumar L Rabara <niravkumar.l.rabara@altera.com> | 2025-04-25 17:26:40 +0300 |
|---|---|---|
| committer | Borislav Petkov (AMD) <bp@alien8.de> | 2025-04-28 13:38:53 +0300 |
| commit | 6dbe3c5418c4368e824bff6ae4889257dd544892 (patch) | |
| tree | f81056a8832ab9d0af9d63fd68bc6c1b2bc486e4 /scripts/generate_rust_target.rs | |
| parent | 4fb7b8fceb0beebbe00712c3daf49ade0386076a (diff) | |
| download | linux-6dbe3c5418c4368e824bff6ae4889257dd544892.tar.xz | |
EDAC/altera: Set DDR and SDMMC interrupt mask before registration
Mask DDR and SDMMC in probe function to avoid spurious interrupts before
registration. Removed invalid register write to system manager.
Fixes: 1166fde93d5b ("EDAC, altera: Add Arria10 ECC memory init functions")
Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@altera.com>
Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Cc: stable@kernel.org
Link: https://lore.kernel.org/20250425142640.33125-3-matthew.gerlach@altera.com
Diffstat (limited to 'scripts/generate_rust_target.rs')
0 files changed, 0 insertions, 0 deletions