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| author | Xingyu Wu <xingyu.wu@starfivetech.com> | 2023-07-17 05:30:34 +0300 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2023-07-19 20:07:48 +0300 |
| commit | bd348ca24d81cca2a27f8ffa12adc8f30f184275 (patch) | |
| tree | c70d6233857bc91f11f4b3ef10cabb76bcea8e28 /scripts/generate_rust_analyzer.py | |
| parent | 06c2afb862f9da8dc5efa4b6076a0e48c3fbaaa5 (diff) | |
| download | linux-bd348ca24d81cca2a27f8ffa12adc8f30f184275.tar.xz | |
dt-bindings: clock: Add StarFive JH7110 PLL clock generator
Add bindings for the PLL clock generator on the JH7110 RISC-V SoC.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions