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| author | Eric Yang <eric.yang@amd.com> | 2024-01-16 22:50:55 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2024-01-29 23:42:52 +0300 |
| commit | f2a905b01c6dcca8ce298316eac4e42f766ce766 (patch) | |
| tree | c0176c0626d597d98ba6855a3e24fc43f3663a15 /scripts/gdb/linux/utils.py | |
| parent | 7fc0d111baad0a65f8341b904937ad2b10cc4f1e (diff) | |
| download | linux-f2a905b01c6dcca8ce298316eac4e42f766ce766.tar.xz | |
drm/amd/display: fix invalid reg access on DCN35 FPGA
[Why]
Unguarded SMU and CLK IP access cause issue on FPGA
[How]
Guard them for FPGA environment
Reviewed-by: Sung joon Kim <sungjoon.kim@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Eric Yang <eric.yang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions