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| author | Tejas Upadhyay <tejas.upadhyay@intel.com> | 2023-06-01 14:09:59 +0300 |
|---|---|---|
| committer | Andi Shyti <andi.shyti@linux.intel.com> | 2023-06-05 12:11:54 +0300 |
| commit | d922b80b1010cd6164fa7d3c197b4fbf94b47beb (patch) | |
| tree | d51b762c2771a216a1816afb57e8dc29f8608339 /scripts/gdb/linux/utils.py | |
| parent | 5c315434fdb6ab43566e6e0f6b9528bb0ad0aca9 (diff) | |
| download | linux-d922b80b1010cd6164fa7d3c197b4fbf94b47beb.tar.xz | |
drm/i915/gt: Add workaround 14016712196
For mtl, workaround suggests that, SW insert a
dummy PIPE_CONTROL prior to PIPE_CONTROL which
contains a post sync: Timestamp or Write Immediate.
Bspec: 72197
V5:
- Remove ret variable - Andi
V4:
- Update commit message, avoid returing cs - Andi/Matt
V3:
- Wrap dummy pipe control stuff in API - Andi
V2:
- Fix kernel test robot warnings
Closes: https://lore.kernel.org/oe-kbuild-all/202305121525.3EWdGoBY-lkp@intel.com/
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230601110959.1715927-1-tejas.upadhyay@intel.com
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions