diff options
| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2025-02-11 13:56:02 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-02-18 12:34:08 +0300 |
| commit | a08903f0b0020cacf60b29d4708d7ebec5b041a4 (patch) | |
| tree | 7696ea789884bfb4aa40e5b83afe17dd00e00226 /scripts/gdb/linux/utils.py | |
| parent | 5a1cb35ba37ada76ae486fbac7b249322dd1a5c3 (diff) | |
| download | linux-a08903f0b0020cacf60b29d4708d7ebec5b041a4.tar.xz | |
clk: renesas: rzg2l: Update error message
Update the error message in `rzg2l_mod_clock_endisable()` to provide
clearer debugging information. Instead of printing only the register
address, include both the `CLK_ON_R(reg)` offset and the corresponding
`clk` name (`%pC`). This enhances readability and aids in debugging
clock enable failures.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250211105603.195905-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions