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authorPhil Edworthy <phil.edworthy@renesas.com>2022-05-03 14:55:47 +0300
committerGeert Uytterhoeven <geert+renesas@glider.be>2022-05-05 13:04:58 +0300
commit96055bf71ab1629cdedff15bcbc04609cfa1f198 (patch)
tree40c9c8016a4a3743faaca528d628bd9353b2c637 /scripts/gdb/linux/utils.py
parent3123109284176b1532874591f7c81f3837bbdc17 (diff)
downloadlinux-96055bf71ab1629cdedff15bcbc04609cfa1f198.tar.xz
dt-bindings: clock: Add r9a09g011 CPG Clock Definitions
Define RZ/V2M (R9A09G011) Clock Pulse Generator module clock outputs (CPG_CLK_ON* registers), and reset definitions (CPG_RST_* registers) in Section 48.5 ("Register Description") of the RZ/V2M Hardware User's Manual (Rev. 1.10, Sep. 2021). Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220503115557.53370-3-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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