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| author | Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> | 2023-02-11 17:36:53 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2023-03-06 12:42:14 +0300 |
| commit | 8b406fd422d568a407a98c2809c0b2c6bdc95be3 (patch) | |
| tree | 2c986a217a3ae218ce116768e04f88c81f22cf77 /scripts/gdb/linux/utils.py | |
| parent | 7502a04dae0e614bc14553e31461e50499bc67aa (diff) | |
| download | linux-8b406fd422d568a407a98c2809c0b2c6bdc95be3.tar.xz | |
clk: renesas: r8a779g0: Add CSI-2 clocks
Add the CSI core clock and the CSI40 and CSI41 module clocks, which are
used by the CSI-2 Interfaces on the Renesas R-Car V4H (R8A779G0) SoC.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230211143655.3809756-2-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions