diff options
| author | Takeshi Kihara <takeshi.kihara.df@renesas.com> | 2023-02-02 04:03:14 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2023-03-06 12:42:14 +0300 |
| commit | 75a2f9734e9bf297959a1e8cf16655a50075f531 (patch) | |
| tree | 025db8d230ed98bd2c6fb0f6b030367b8587efdd /scripts/gdb/linux/utils.py | |
| parent | fe15c26ee26efa11741a7b632e9f23b01aca4cc6 (diff) | |
| download | linux-75a2f9734e9bf297959a1e8cf16655a50075f531.tar.xz | |
clk: renesas: cpg-mssr: Update MSSR register range for R-Car V4H
The SRCR, SRSTCLR, MSTPCR and MSTPSR registers for R-Car V4H (R8A779G0)
each have registers up to offset 0x74.
Update the corresponding arrays.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/87a61wanfx.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions