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| author | Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2019-12-08 21:05:25 +0300 |
|---|---|---|
| committer | Kevin Hilman <khilman@baylibre.com> | 2019-12-11 22:26:27 +0300 |
| commit | 6d549ff55c3717c4f5b0202a22c7404395559cec (patch) | |
| tree | 505108bd40921db61ea68c08c0e4f9b462e19734 /scripts/gdb/linux/utils.py | |
| parent | c4ac5c37a4a5c5ce94f70542d006568bd4b7d685 (diff) | |
| download | linux-6d549ff55c3717c4f5b0202a22c7404395559cec.tar.xz | |
ARM: dts: meson8b: add the DDR clock controller
Add the DDR clock controller and pass it's DDR_CLKID_DDR_PLL to the main
(HHI) clock controller as "ddr_clk". The "ddr_clk" is used as one of the
inputs for the audio clock muxes.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions