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| author | Phil Edworthy <phil.edworthy@renesas.com> | 2022-05-03 14:55:53 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-05-05 13:12:33 +0300 |
| commit | 63804400f2a5ababe596b4ec908321d6b54f45aa (patch) | |
| tree | 32cb17c6f483ef041f27e3df15f652b0f692c13e /scripts/gdb/linux/utils.py | |
| parent | 75b0ad42ccd9a87873e91598116471d9991b09ea (diff) | |
| download | linux-63804400f2a5ababe596b4ec908321d6b54f45aa.tar.xz | |
clk: renesas: rzg2l: Make use of CLK_MON registers optional
The RZ/V2M SoC doesn't use CLK_MON registers, so make them optional.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220503115557.53370-9-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions