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authorJim Quinlan <james.quinlan@broadcom.com>2024-08-16 01:57:20 +0300
committerKrzysztof Wilczyński <kwilczynski@kernel.org>2024-09-04 16:59:28 +0300
commit30eb2080fe2043c3e61c1ae4bb6917800b10fb08 (patch)
treeeaf63abfeacdc9d2410c11e65dba494e5bfa2f55 /scripts/gdb/linux/utils.py
parent8201360218c6a42b3f7ff03d8908bd345e3620f4 (diff)
downloadlinux-30eb2080fe2043c3e61c1ae4bb6917800b10fb08.tar.xz
PCI: brcmstb: PCI: brcmstb: Make HARD_DEBUG, INTR2_CPU_BASE offsets SoC-specific
Do preparatory work for the 7712 SoC, which is introduced in a future commit. Our HW design has changed two register offsets for the 7712, where previously it was a common value for all Broadcom SoCs with PCIe cores. Specifically, the two offsets are to the registers HARD_DEBUG and INTR2_CPU_BASE. Link: https://lore.kernel.org/linux-pci/20240815225731.40276-8-james.quinlan@broadcom.com Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Stanimir Varbanov <svarbanov@suse.de>
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