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| author | Heyi Guo <guoheyi@huawei.com> | 2020-02-25 12:00:23 +0300 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2020-03-08 17:25:46 +0300 |
| commit | 04d80dbe858d801efbecf3e5172b31b0a3757308 (patch) | |
| tree | 6a3bb01026b1cb74232f7e1a121845814388d7a0 /scripts/gdb/linux/utils.py | |
| parent | 47beed513a85b3561e74cbb4dd7af848716fa4e0 (diff) | |
| download | linux-04d80dbe858d801efbecf3e5172b31b0a3757308.tar.xz | |
irqchip/gic-v3-its: Fix access width for gicr_syncr
GICR_SYNCR is a 32bit register, so it is better to access it with
32bit access width, though we have not seen any real problem.
Signed-off-by: Heyi Guo <guoheyi@huawei.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20200225090023.28020-1-guoheyi@huawei.com
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions