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| author | Rob Clark <robdclark@gmail.com> | 2014-06-25 17:54:36 +0400 |
|---|---|---|
| committer | Rob Clark <robdclark@gmail.com> | 2014-08-04 19:55:28 +0400 |
| commit | 034fbcc3d8a5dff5d3df5a4ad6bf9cc0b01bd970 (patch) | |
| tree | 9c27803c6c44f446ed71680fb058927bbc08dd98 /scripts/gdb/linux/utils.py | |
| parent | 89301471e6bf942c026d6ebfcbc9a6a937cc6865 (diff) | |
| download | linux-034fbcc3d8a5dff5d3df5a4ad6bf9cc0b01bd970.tar.xz | |
drm/msm: hdmi phy 8960 phy pll
On downstream kernel the clk driver directly bangs hdmi phy registers.
For upstream kernel, we need to model this as a clock and register with
the clock framework.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions