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| author | Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com> | 2021-03-12 11:07:03 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2021-03-13 03:58:36 +0300 |
| commit | c3b8e07909dbe67b0d580416c1a5257643a73be7 (patch) | |
| tree | dc53529a132a9acf2f574fd6bc457ae86f014e13 /scripts/gdb/linux/timerlist.py | |
| parent | 2e5de7e0c8d2caa860e133ef71fc94671cb8e0bf (diff) | |
| download | linux-c3b8e07909dbe67b0d580416c1a5257643a73be7.tar.xz | |
net: dsa: mt7530: setup core clock even in TRGMII mode
A recent change to MIPS ralink reset logic made it so mt7530 actually
resets the switch on platforms such as mt7621 (where bit 2 is the reset
line for the switch). That exposed an issue where the switch would not
function properly in TRGMII mode after a reset.
Reconfigure core clock in TRGMII mode to fix the issue.
Tested on Ubiquiti ER-X (MT7621) with TRGMII mode enabled.
Fixes: 3f9ef7785a9c ("MIPS: ralink: manage low reset lines")
Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'scripts/gdb/linux/timerlist.py')
0 files changed, 0 insertions, 0 deletions