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| author | Zhang Rui <rui.zhang@intel.com> | 2023-10-19 06:04:33 +0300 |
|---|---|---|
| committer | Zhang Rui <rui.zhang@intel.com> | 2023-10-24 08:38:09 +0300 |
| commit | 0e3f10e6aa97b0134b526ec9cdc3ccdac2239b43 (patch) | |
| tree | 3214aeb9752b60f6eab2014bbf49826312fd824e /scripts/gdb/linux/interrupts.py | |
| parent | 37f68a2940558b4f6f8e51b7b1d00f084b4bdde2 (diff) | |
| download | linux-0e3f10e6aa97b0134b526ec9cdc3ccdac2239b43.tar.xz | |
tools/power/turbostat: Add MSR_CORE_C1_RES support for spr_features
Add MSR_CORE_C1_RES support for spr_features because both Sapphirerapids
and Emeraldrapids support this MSR.
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Diffstat (limited to 'scripts/gdb/linux/interrupts.py')
0 files changed, 0 insertions, 0 deletions