diff options
| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2021-11-17 03:26:01 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-11-19 13:36:27 +0300 |
| commit | e7d960cd6afd56d8c6d4408b6b8a59c91baafcc2 (patch) | |
| tree | 9919aa95510fab952592a181f12ccb3a21dfddfd /scripts/gdb/linux/clk.py | |
| parent | d6dabaf678971733da56b2e84793348f714d42ff (diff) | |
| download | linux-e7d960cd6afd56d8c6d4408b6b8a59c91baafcc2.tar.xz | |
clk: renesas: r9a07g044: Add RSPI clock and reset entries
Add RSPI{0,1,2} clock and reset entries to CPG driver.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20211117002601.17971-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'scripts/gdb/linux/clk.py')
0 files changed, 0 insertions, 0 deletions