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| author | Zhenyu Wang <zhenyuw@linux.intel.com> | 2019-04-16 11:50:34 +0300 |
|---|---|---|
| committer | Zhenyu Wang <zhenyuw@linux.intel.com> | 2019-04-16 11:50:34 +0300 |
| commit | 95d002e0a34cb0f238abb39987f9980f325d8332 (patch) | |
| tree | b8ed70572a55b4e67410f906159f86e8aabb0f6a /scripts/decodecode | |
| parent | d57b39e3ee3cdb4b00452090e386d197980cefc9 (diff) | |
| parent | 28d618e9ab86f26a31af0b235ced55beb3e343c8 (diff) | |
| download | linux-95d002e0a34cb0f238abb39987f9980f325d8332.tar.xz | |
Merge tag 'drm-intel-next-2019-04-04' into gvt-next
Merge back drm-intel-next for engine name definition refinement
and 54939ea0bd85 ("drm/i915: Switch to use HWS indices rather than addresses")
that would need gvt fixes to depend on.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Diffstat (limited to 'scripts/decodecode')
| -rwxr-xr-x | scripts/decodecode | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/scripts/decodecode b/scripts/decodecode index 9cef558528aa..ba8b8d5834e6 100755 --- a/scripts/decodecode +++ b/scripts/decodecode @@ -60,6 +60,13 @@ case $width in 4) type=4byte ;; esac +if [ -z "$ARCH" ]; then + case `uname -m` in + aarch64*) ARCH=arm64 ;; + arm*) ARCH=arm ;; + esac +fi + disas() { ${CROSS_COMPILE}as $AFLAGS -o $1.o $1.s > /dev/null 2>&1 |