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| author | Pierre-Louis Bossart <pierre-louis.bossart@linux.dev> | 2025-02-27 17:06:01 +0300 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2025-03-10 10:01:18 +0300 |
| commit | 3e3ae0c8fccc51021136b192ec88e94a1bc5704c (patch) | |
| tree | 401f15530b43e6b8c183f4956f2b8deb22ace091 /scripts/clang-tools/gen_compile_commands.py | |
| parent | 3641c6392695b0846e80a4c1245d7139c8ed7d48 (diff) | |
| download | linux-3e3ae0c8fccc51021136b192ec88e94a1bc5704c.tar.xz | |
soundwire: cadence: add BTP support for DP0
The register definitions are missing a BULK_ENABLE bitfield which must
be set for DP0.
In addition, the existing mapping from PDI to Data Port is 1:1. That's
fine for PCM streams which are by construction in one direction
only. The BTP/BRA protocol is bidirectional and relies on DP0 only,
which breaks the 1:1 mapping. DP0 MUST be mapped to both PDI0 and
PDI1, with PDI0 taking care of the TX direction and PDI1 of the RX
direction.
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.dev>
Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: Liam Girdwood <liam.r.girdwood@intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Tested-by: shumingf@realtek.com
Link: https://lore.kernel.org/r/20250227140615.8147-3-yung-chuan.liao@linux.intel.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'scripts/clang-tools/gen_compile_commands.py')
0 files changed, 0 insertions, 0 deletions