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authorIra Weiny <ira.weiny@intel.com>2021-05-28 03:49:18 +0300
committerDan Williams <dan.j.williams@intel.com>2021-06-06 03:24:04 +0300
commit07d62eac422c5c8aec6ec1dacdc27423334b2d17 (patch)
treeb1e526307abb713754a080f27f5ff7119c5fe492 /rust/helpers/workqueue.c
parent6630d31c912ed2dfbc035caf0f54709b50ce779e (diff)
downloadlinux-07d62eac422c5c8aec6ec1dacdc27423334b2d17.tar.xz
cxl/pci: Introduce cxl_decode_register_block()
Each register block located in the DVSEC needs to be decoded from 2 words, 'register offset high' and 'register offset low'. Create a function, cxl_decode_register_block() to perform this decode and return the bar, offset, and register type of the register block. Then use the values decoded in cxl_mem_map_regblock() instead of passing the raw registers. Signed-off-by: Ira Weiny <ira.weiny@intel.com> Link: https://lore.kernel.org/r/20210528004922.3980613-2-ira.weiny@intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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