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| author | Alex Deucher <alexander.deucher@amd.com> | 2020-08-19 02:24:03 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-08-26 23:40:18 +0300 |
| commit | f8646661f713fb7d33ebe404d418bd3fa55c383e (patch) | |
| tree | 473f046a55f7336acdf0950ae8956bb8424d8441 /net/sched/sch_cbq.c | |
| parent | b04e48bcac08ae900b5ea77a86f90356f51cf26c (diff) | |
| download | linux-f8646661f713fb7d33ebe404d418bd3fa55c383e.tar.xz | |
drm/amdgpu: fix up DCHUBBUB_SDPIF_MMIO_CNTRL_0 handling
Properly define this register using a relative offset rather
than an absolute offset and use the proper SOC15 macros to
access it. It's also DCN, not DCE, so remove it from the
DCE12 header.
No functional change.
Acked-by: Nirmoy Das <nirmoy.das@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'net/sched/sch_cbq.c')
0 files changed, 0 insertions, 0 deletions