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| author | Andre Przywara <andre.przywara@arm.com> | 2025-03-07 03:26:26 +0300 |
|---|---|---|
| committer | Chen-Yu Tsai <wens@csie.org> | 2025-03-12 06:58:11 +0300 |
| commit | f3dabb29f0ca44f2053c0c3943ca6f47b248d348 (patch) | |
| tree | f28aaace46d88aa7b13bc1d88c76d908ffa6c427 /lib/test_fortify/write_overflow-strncpy.c | |
| parent | 00bc60ea24a7b31da97a3b8a833711491c285ae4 (diff) | |
| download | linux-f3dabb29f0ca44f2053c0c3943ca6f47b248d348.tar.xz | |
clk: sunxi-ng: a523: add bus clock gates
Add the various bus clock gates that control access to the devices'
register interface.
These clocks are each just one bit, typically the lower bits in some "BGR"
(Bus Gate / Reset) registers, for each device group: one for all UARTs,
one for all SPI interfaces, and so on.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://patch.msgid.link/20250307002628.10684-13-andre.przywara@arm.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Diffstat (limited to 'lib/test_fortify/write_overflow-strncpy.c')
0 files changed, 0 insertions, 0 deletions