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| author | Andre Przywara <andre.przywara@arm.com> | 2024-10-01 13:50:16 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2024-12-05 15:53:36 +0300 |
| commit | db8abd60150ec0d7afb739ce60bd82a31b90a265 (patch) | |
| tree | 94abfb78c988e05eab0ddb2e235cf43e37368bc5 /lib/logic_pio.c | |
| parent | ee31de294ec86a2ddd1d15fd957fb98cb9c18764 (diff) | |
| download | linux-db8abd60150ec0d7afb739ce60bd82a31b90a265.tar.xz | |
clk: sunxi-ng: d1: Fix PLL_AUDIO0 preset
[ Upstream commit e0f253a52ccee3cf3eb987e99756e20c68a1aac9 ]
To work around a limitation in our clock modelling, we try to force two
bits in the AUDIO0 PLL to 0, in the CCU probe routine.
However the ~ operator only applies to the first expression, and does
not cover the second bit, so we end up clearing only bit 1.
Group the bit-ORing with parentheses, to make it both clearer to read
and actually correct.
Fixes: 35b97bb94111 ("clk: sunxi-ng: Add support for the D1 SoC clocks")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Link: https://patch.msgid.link/20241001105016.1068558-1-andre.przywara@arm.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'lib/logic_pio.c')
0 files changed, 0 insertions, 0 deletions