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| author | Jouni Högander <jouni.hogander@intel.com> | 2026-05-15 12:57:56 +0300 |
|---|---|---|
| committer | Jouni Högander <jouni.hogander@intel.com> | 2026-05-18 09:06:40 +0300 |
| commit | fed4921503a8a346ea4e6826eee7658f480341ec (patch) | |
| tree | b1ce470ccd1c4a1abcec82bf9f997cfd58cc1f4a /include | |
| parent | c3fe899fbeac86ea4a5ca9dd845b2cbc0da46249 (diff) | |
| download | linux-fed4921503a8a346ea4e6826eee7658f480341ec.tar.xz | |
drm/i915/psr: Apply SDP on prior scanline workaround for Xe3p
In Xe3p there is an HW optimization done. When there is an SU triggered in
Capture state, Link will be kept ON post Capture CRC SDP. Before valid SU
pixels Intel source will transmit dummy pixels. Some TCONS are improperly
considering these dummy pixels as a valid pixel data. Prior Xe3p link was
was turned off even if there was SU triggered in capture state and no dummy
pixels were transmitted. These dummy pixels are problem only if SDP on
prior scanline is used and Early Transport is not in use. The workaround is
to start SU area always at scanline 0.
v2: use intel_display_wa
Bspec: 74741, 79482
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20260515095756.2799483-5-jouni.hogander@intel.com
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions