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authorKrishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>2025-10-13 13:53:29 +0300
committerBjorn Andersson <andersson@kernel.org>2025-10-27 20:05:40 +0300
commitfc0ed54869be3a40c92879411b6db553d271de4d (patch)
tree978e2431732a653c603e636de96e9f474a16294e /include
parent367c2f473f5f5a84cdf633df96e0f9b4a16e443d (diff)
downloadlinux-fc0ed54869be3a40c92879411b6db553d271de4d.tar.xz
arm64: dts: qcom: sm8550: Add opp-level to indicate PCIe data rates
The existing OPP table for PCIe is shared across different link configurations such as data rates 8GT/s x2 and 16GT/s x1. These configurations often operate at the same frequency, allowing them to reuse the same OPP entries. However, 8GT/s and 16 GT/s may have different RPMh votes which cannot be represented accurately when sharing a single OPP. To address this, introduce an `opp-level` to indicate the PCIe data rate and uniquely differentiate OPP entries even when the frequency is the same. Although this platform does not currently suffer from this issue, the change is introduced to support unification across platforms. Append the opp level to name of the opp node to indicate both frequency and level. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Acked-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://lore.kernel.org/r/20251013-opp_pcie-v5-2-eb64db2b4bd3@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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