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authorvamshi gajjela <vamshigajjela@google.com>2025-12-11 16:32:27 +0300
committerMartin K. Petersen <martin.petersen@oracle.com>2025-12-17 05:13:27 +0300
commite642331c942003f58dba6e33c8ee93402211b7b6 (patch)
treed060ba09b2300fda51a4de05b84c65b8c463595c /include
parent7011e8aafe8c8fcc1c6f8bfcc6796f4530428e13 (diff)
downloadlinux-e642331c942003f58dba6e33c8ee93402211b7b6.tar.xz
scsi: ufs: core: mcq: Use ufshcd_rmwl() instead of open-coding it
Currently, ufshcd_mcq_enable_esi() manually implements a read-modify-write sequence using ufshcd_readl() and ufshcd_writel(). It also utilizes a hardcoded magic number (0x2) for the enable bit. Use ufshcd_rmwl() helper, replace the magic number with the ESI_ENABLE macro to improve code readability. No functional change intended. Signed-off-by: vamshi gajjela <vamshigajjela@google.com> Reviewed-by: Bart Van Assche <bvanassche@acm.org> Link: https://patch.msgid.link/20251211133227.4159394-1-vamshigajjela@google.com Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Diffstat (limited to 'include')
-rw-r--r--include/ufs/ufshci.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/ufs/ufshci.h b/include/ufs/ufshci.h
index d36df24242a3..806fdaf52bd9 100644
--- a/include/ufs/ufshci.h
+++ b/include/ufs/ufshci.h
@@ -288,6 +288,7 @@ enum {
/* REG_UFS_MEM_CFG - Global Config Registers 300h */
#define MCQ_MODE_SELECT BIT(0)
+#define ESI_ENABLE BIT(1)
/* CQISy - CQ y Interrupt Status Register */
#define UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS 0x1